1. Field of the Invention
This invention relates to an improved Static Random Access Memory (SCRAM) cell and more particularly to stable cell with only one word line.
2. Description of the Background
Typical prior art CMOS SRAM cells have a six-transistor typology, such as that shown in FIG. 1. Two P channel field effect transistors (PPETs) P1 and P2 act as pull up transistors and two N channel field effect transistors (NFETs) N1 and N2 act as pull down transistors. Two NFETs N3 and N4 serve as pass gates to control access to the cell for reading and writing to the cell. These pass gates N3 and N4 are connected to a word line WL. P1 and N1 form an inverter and P2 and N2 form another inverter. As shown these invertors are cross-coupled to form a bi-stable cell.
An SRAM array has n rows and m columns of SRAM cells with cells of a row sharing a single word line WL and cells of a column sharing a pair of bit lines BLL and BLR. During standby, all of the word lines WL are low (i.e., at GND) and all bit lines are biased to the voltage level of the power supply Vdd. Thus, the pass-gate transistors of each cell are shut off. A cell state representing a 1 data bit, for example, is established with P1 and N2 on and P2 and N1 off so that the node L at the left of the cell is high (Vdd) and the node R at the right of the cell is low (GND). With P1 and N2 off and P2 and N1 on, node L is low and node R is high. During access time to the SRAM array a row is selected by driving its word line WL high to Vdd, which turns on half of the pass gates connected to that word line, namely, those connected to a high node. Thus, for each cell along a word line, one pass gate is turned on.
During a read access, a cell in a selected column, where its bit lines precharge devices are turned off, pulls down one of the bit lines (BL or BR) from its pre-charged high state (Vdd) by the “ON” passgate of the full selected cell (one that is selected in both the word and column dimension). A sense amplifier detects the differential voltage between the bit lines and generates an output. The cells along a selected word line likewise generate a differential voltage, but these signals are ignored. These cells along a selected word line that are not selected by the columns are commonly referred to as “half selected” cells. Unselected columns could have their bit line precharge devices either turned off or stayed on, depending on the design preference.
High performance designs, such as for cache where read and write operations are performed within a short clock cycle, cell beta ratios that are typically in a range between 2.2 and 3.5 in order to avoid unintended changes in the state of a cell due to a so called “half-selected cell disturbance”. The beta ratio is a function of the ratio of the channel resistance of the pass gate transistor to the channel resistance of the pull down transistor. Half-selected cell disturbance occurs when a word line connected to a memory cell of unselected columns with bit lines biased to a predetermined Vdd is activated. This causes the body voltage of a pass-gate transistor of a non-selected cell to be more conductive than the cell pull down transistor, there by causing the ground state node (“0”node) to switch states and disrupt the state of the memory cell.
In fast switching environments a high beta ratio improves the margin preventing half-selected cell disturbances. However a higher-beta ratio results in decreased cell performance, such as lower write. Particularly, sub 100 nm silicon technologies are having increased problems with cell SRAM cell stability when trying to write to the cells at high rates due to the inherent variations in individual cell beta ratios as a result to limitations in the degree to which device channel parameters can be controlled at these extremely small devices sizes.
Adding additional transistors to the basic six-transistor SRAM cell have been proposed in the prior art in order to prevent half-selected cell disturbance by providing separate access paths for reading and writing. However these prior art proposals have not proven satisfactory. Particularly, as they employ two separate word lines, one for writing and one for reading.